2002 Microchip Technology Inc.
Preliminary
DS30485A-page 215
PIC18FXX39
CONTROL OPERATIONS
BC
BN
BNC
BNN
BNOV
BNZ
BOV
BRA
BZ
CALL
CLRWDT
DAW
GOTO
NOP
POP
PUSH
RCALL
RESET
RETFIE
RETLW
RETURN
SLEEP
n
n, s
n
n
s
k
s
Branch if Carry
Branch if Negative
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Overflow
Branch Unconditionally
Branch if Zero
Call subroutine 1st word
2nd word
Clear Watchdog Timer
Decimal Adjust WREG
Go to address 1st word
2nd word
No Operation
Pop top of return stack (TOS)
Push top of return stack (TOS)
Relative Call
Software device RESET
Return from interrupt enable
Return with literal in WREG
Return from Subroutine
Go into Standby mode
1 (2)
2
1 (2)
2
1
2
1
2
1
2
1
1110
1101
1110
1111
0000
1110
1111
0000
1111
0000
1101
0000
0010
0110
0011
0111
0101
0001
0100
0nnn
0000
110s
kkkk
0000
1111
kkkk
0000
xxxx
0000
1nnn
0000
1100
0000
nnnn
kkkk
0000
kkkk
0000
xxxx
0000
nnnn
1111
0001
kkkk
0001
0000
nnnn
kkkk
0100
0111
kkkk
0000
xxxx
0110
0101
nnnn
1111
000s
kkkk
001s
0011
None
TO, PD
C
None
All
GIE/GIEH,
PEIE/GIEL
None
TO, PD
4
TABLE 21-2:
PIC18FXXX INSTRUCTION SET (CONTINUED)
Mnemonic,
Operands
Description
Cycles
16-Bit Instruction Word
Status
Affected
Notes
MSb
LSb
Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value
present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an
external device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
4: Some instructions are 2-word instructions. The second word of these instructions will be executed as a NOP, unless the
first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory
locations have a valid instruction.
5: If the Table Write starts the write cycle to internal memory, the write will continue until terminated.
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